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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
Features
ESD Protect for 2 high-speed I/O channels Provide ESD protection for each channel to
IEC 61000-4-2 (ESD) 18kV (air), 14kV (contact) IEC 61000-4-4 (EFT) (5/50ns) Level-3, 20A for I/O, 80A for Power IEC 61000-4-5 (Lightning) 6.5A (8/20s)
AZC015-02N may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 ( 15kV air, 8kV contact discharge).
Circuit Diagram
4
5V operating voltage Low capacitance : 1.3pF typical Fast turn-on and Low clamping voltage Array of surge rated diodes with internal equivalent TVS diode Small package saves board space Solid-state silicon-avalanche and active circuit triggering technology
2
3
Applications
1
USB2.0 Power and Data lines protection Notebook and PC Computers Monitors and Flat Panel Displays IEEE 1394 Firewire Ports Video Graphics Cards SIM ports
Description
AZC015-02N is a high performance and low cost design which includes surge rated diode arrays to protect high speed data interfaces. The AZC015-02N family has been specifically designed to protect sensitive components, which are connected to data and transmission lines, from over-voltage caused by Electrostatic Discharging (ESD), Electrical Fast Transients (EFT), and Lightning. AZC015-02N is a unique design which includes surge rated, low capacitance steering diodes and a unique design of clamping cell which is an equivalent TVS diode in a single package. During transient conditions, the steering diodes direct www..com the transient to either the power supply line or to the ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components.
Pin Configuration
VDD 4 I/O 2 3
1 GND
2 I/O 1
JEDEC SOT143-4L (Top View)
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETER Peak Pulse Current (tp =8/20s) Operating Supply Voltage (VDD-GND) ESD per IEC 61000-4-2 (Air)(I/O to GND) ESD per IEC 61000-4-2 (Contact) (I/O to GND) ESD per IEC 61000-4-2(Air)(VDD-GND) ESD per IEC 61000-4-2(Contact) (VDD-GND) Lead Soldering Temperature Operating Temperature Storage Temperature DC Voltage at any I/O pin PARAMETER Reverse Stand-Off Voltage Reverse Leakage Current Channel Leakage Current Reverse Breakdown Voltage Forward Voltage Clamping Voltage ESD Clamping Voltage -I/O ESD Clamping Voltage -VDD ESD Dynamic Turn-on Resistance -I/O ESD Dynamic Turn-on Resistance -VDD Channel Input Capacitance
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PARAMETER IPP VDC VESD_I/O VESD_VDD TSOL TOP TSTO VIO
RATING 6.5 6 18 14 30 30 260 (10 sec.) -55 to +85 -55 to +150 (GND - 0.5) to (VDD + 0.5) MIN TYP MAX 5 5 1 6 0.8 8.1 12.5 9 0.35 0.2 1.3 0.12 0.05 1.6 0.14 0.07 9 1 9
UNITS A V kV kV
o o o
C C C
V UNITS V A A V V V V V pF pF pF
SYMBOL VRWM ILeak ICH_Leak VBV VF VCL Vclamp_io Vclamp_VDD Rdynamic_io
ELECTRICAL CHARACTERISTICS CONDITIONS Pin 4 to pin 1, T=25 oC VRWM = 5V, T=25 oC, Pin 4 to pin 1 VPin 4 = 5V, VPin 1 = 0V, T=25 oC, VCH = 0 ~ 5V IBV = 1mA, T=25 oC Pin 4 to Pin 1 IF = 15mA, T=25 oC Pin 1 to Pin 4 IPP=5A, tp=8/20s, T=25 oC Any Channel pin to Ground IEC 61000-4-2 +6kV, T=25 oC, Contact mode, Any Channel pin to Ground IEC 61000-4-2 +6kV, T=25 oC, Contact mode, VDD pin to Ground IEC 61000-4-2 0~+6kV, T=25 oC, Contact mode, Any Channel pin to Ground IEC 61000-4-2 0~+6kV, T=25 oC, Contact mode, VDD pin to Ground Vpin4 = 5V, Vpin1 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC, Any Channel pin to Ground Vpin4 = 5V, Vpin1 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Between Channel pins Vpin4 = 5V, Vpin1 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Channel_x pin to Ground - Channel_y pin to Ground
2
Rdynamic_VDD CIN CCROSS CIN
Channel to Channel Input Capacitance Variation of Channel Input Capacitance
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
Typical Characteristics
Power Derating Curve 110 100 % of Rated Power or IPP 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150
Clamping Voltage (V) 12 11 10 9 8 7 6 5 4 3 2 1 0 4.5 5.0 5.5 6.0 6.5
I/O pin to GND pin Waveform Parameters: tr=8s td=20s
Clamping Voltage vs. Peak Pulse Current
7.0
7.5
Ambient Temperature, TA (oC)
Peak pulse Current (A)
Forward Voltage vs. Forward Current 4.0 3.5 Forward Voltage (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5
I/O pin to GND pin Waveform Parameters: tr=8s td=20s
Typical Variation of CIN vs. VIN 2.0 1.8 Input Capacitance (pF) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
VDD = 5V, GND = 0V, f = 1MHz, T=25 oC,
5.0
5.5
6.0
6.5
7.0
7.5
0.0
0
1
2
3
4
5
Peak pulse Current (A)
Transmission Line Pulsing (TLP) Current (A)
Typical Variation of CIN vs. Temp 1.50 1.45 Input Capacitance (pF) 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 20
VDD = 5V, GND = 0V, VIN = 2.5V, f = 1MHz,
Input Voltage (V)
Transmission Line Pulsing (TLP) Measurement 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 Transmission Line Pulsing (TLP) Voltage (V)
V_pulse Pulse from a transmission line TLP_I
100ns
+ TLP_V DUT
I/O to GND
40
Temperature (oC)
60
80
100
120
Transmission Line Pulsing (TLP) Current (A)
Transmission Line Pulsing (TLP) Measurement 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 Transmission Line Pulsing (TLP) Voltage (V)
V_pulse Pulse from a transmission line TLP_I
100ns
+ TLP_V DUT
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VDD to GND
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
Applications Information
A. Design Considerations
The ESD protection scheme for system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D2 are general used to protect data line from ESD stress pulse. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (IESD1) will pass through the ESD current path1. Thus, the ESD clamping voltage VCL of data line can be described as follow: VCL = Fwd voltage drop of D1 + supply voltage of VDD rail + L1 x d(IESD1)/dt + L2 x d(IESD1)/dt Where L1 is the parasitic inductance of data line, and L2 is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30A in 1ns. Here d(IESD1)/dt can be approximated by IESD1/t, or 30/(1x10-9). So
just 10nH of total parasitic inductance (L1 and L2 combined) will lead to over 300V increment in VCL! Besides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. The AZC015-02N has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (IESD2) will be directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path2). The clamping voltage VCL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current.
power-rail ESD clamp ing circuit
AZC015-02N
L2
I ESD2 D1 I ESD1
VDD rail
+
Vp
L1
data line
_
VESD
+
Protected IC
D2
V CL
_ GND rail
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ESD current path 1 (I ESD1) ESD current path 2 (I ESD2)
Fig. 1
Application of positive ESD pulse between data line and GND rail.
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
B. Device Connection
The AZC015-02N is designed to protect two data lines and power rails from transient over-voltage (such as ESD stress pulse). The device connection of AZC015-02N is shown in the Fig. 2. In Fig. 2, the two protected data lines are connected to the ESD protection pins (pin2 and pin3) of AZC015-02N. The ground pin (pin1) of AZC015-02N is a negative reference pin. This pin should be directly connected to the GND rail of PCB (Printed Circuit Board). To get minimum parasitic inductance, the path length should keep as short as possible. In addition, the power pin (pin 4) of AZC015-02N is a positive reference pin. This pin should directly connect to the VDD rail of PCB. When pin 4 of AZC015-02N is connected to the VDD rail, the leakage current of ESD
protection pin of AZC015-02N becomes very small. Because the pin 4 of AZC015-02N is directly connected to VDD rail, the VDD rail also can be protected by the power-rail ESD clamped circuit (not shown) of AZC015-02N. AZC015-02N can provide protection for 2 I/O signal lines simultaneously. If the number of I/O signal lines is less than 2, the unused I/O pins can be simply left as NC pins. In some cases, systems are not allowed to be reset or restart after the ESD stress directly applying at the I/O-port connector. Under this situation, in order to enhance the sustainable ESD Level, a 0.1F chip capacitor can be added between the VDD and GND rails. The place of this chip capacitor should be as close as possible to the AZC015-02N.
VDD rail GND rail
1 4
*Optional 0.1F Chip Cap.
AZC015-02N
2
3
To I/O-port Connector
I/O 1
I/O 1
data line
I/O 2
To Protected IC
data line
I/O 2
Fig. 2
Data lines and power rails connection of AZC015-02N.
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
C. Applications
1. Universal Serial Bus (USB) ESD Protection The AZC015-02N can be used to protect the USB port on the monitors, computers, peripherals or portable systems. The ESD protection scheme for single USB ports is shown in Fig. 3. In the Fig.3, the voltage bus (VBUS) of USB port is connected to the power pin (pin 4) of AZC015-02N. Each data line (D+/D-) of USB port is connected to the ESD protection pin (pin2/pin3)
of AZC015-02N. When ESD voltage pulse appears on the data line, the ESD pulse current will be conducted by AZC015-02N away from the USB controller chip. In addition, the ESD pulse current also can be conducted by AZC015-02N away from the USB controller chip when the ESD voltage pulse appears on the voltage bus (VBUS) of USB port. Therefore, the data lines (D+/D-) and voltage bus (VBUS) of two USB ports are complementally protected with an AZC015-02N.
V BUS
1 4 AZC015-02N
USB Controller
2
3
VBUS D+
CT
CT RT RT USB Port
D_
GND
GND
Fig. 3
ESD Protection scheme for single USB ports by using AZC015-02N.
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
2. Audio Interface ESD Protection For the audio interface, the Right/Left channels should be protected from the ESD stress. The AZC015-02N can be used for the audio interface ESD protection. The ESD protection scheme for audio interface is shown in the Fig. 4. In the Fig. 4, the Right and Left channels of audio connector are connected to ESD protection pins (such as pin 2 and pin 3) of AZC015-02N. For the power pin (pin 4) of
AZC015-02N, it should directly connect to the VDD power supply. As well, for the ground pin (pin 1) of AZC015-02N, it should directly connect to the Ground plate. When ESD voltage pulse appears on the Right/Left channel of audio connector, the ESD pulse current will be discharged by AZC015-02N. Therefore, the Right/Left channels of audio chip are complementally protected with an AZC015-02N.
1
4
VDD
AZC015-02N
GND
Audio Chip
Right Channel Left Channel
2
3
Audio Connector
Fig. 4
ESD Protection scheme for audio interface by using AZC015-02N.
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
Mechanical Details
SOT143-4L PACKAGE DIAGRAMS TOP VIEW
PACKAGE DIMENSIONS
SIDE VIEW
END VIEW
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
LAND LAYOUT
A A
Dimensions Index
F E C C1 B
Millimeter 1.00 1.40 1.40 1.92 1.72 2.20 0.80 3.60
Inches 0.039 0.055 0.055 0.076 0.068 0.087 0.031 0.141
A
D
A1 B C C1 D
A1
A
E F
Notes: This LAND LAYOUT is for reference purposes only. Please consult your manufacturing partners to ensure your company's PCB design guidelines are met.
MARKING CODE
4 3
Part Number
Marking Code
C03XY C03X
1 2
AZC015-02N (Rohs part) AZC015-02N (Green part)
C03XY
C03 = Device Code X = Date Code Y = Control Code
C09XY
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AZC015-02N
Low Capacitance ESD Protection Array For High Speed Data Interfaces
Revision History Revision Revision 2007/02/02 Revision 2007/05/15 Revision 2007/12/17 Original Release. Update the Marking Code from C03X to C03XY. 1. Add the Absolute Maximum Ratings of VDD-GND ESD Level, VESD_VDD. 2. Update the maximum Reverse Leakage Current, ILeak, value from 2uA to 5uA. 3. Add the parameters of Vclamp_VDD, Rdynamic_io, Rdynamic_VDD. 4. Add the TLP curve of VDD to GND. 5. Add the maximum value of VBV. Add marking code for the Green part. Modification Description
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